This invention relates to phase-locked loops (PLLs). More particularly, this invention relates to PLLs with improved retiming circuits.
PLLs are widely used in many applications. Typically, PLLs output one or more clock signals locked to both the phase and frequency of a reference clock. PLLs lock the output clock(s) to the reference clock by adjusting the phase and frequency of a PLL internal oscillator.
In one PLL implementation, sometimes referred to as a frequency-multiplying PLL, the PLL adjusts the frequency of the internal oscillator (fOSC) to a frequency equal to the reference clock frequency (fREF) multiplied by n (i.e., fOSC=n*fREF). The PLL locks the phase of the internal oscillator to the reference clock. A clock output by the internal oscillator is frequency divided by n before the divided clock is compared to the reference clock by a phase/frequency detector.
Frequency dividing a clock output by a PLL oscillator produces spurs (i.e., unwanted frequency components) in the frequency spectrum of the divided clock. These spurs undesirably modulate the output of the phase/frequency detector, which increases the total jitter produced by the PLL and therefore degrades the integrity of the PLL output clock(s). Some PLLs use retiming circuits to reduce amplitudes of the spurs. A PLL retiming circuit typically receives the divided clock as input, and outputs a retimed clock for comparison to the reference clock.
Conventional retiming circuits sample the frequency-divided clock with the PLL oscillator clock. This produces a retimed clock with reduced spur levels, but can cause the retimed clock to be erroneous when the sampling occurs during a logic transition of the divided clock (e.g., a transition from logic “0” to logic “1”). Particularly, samples taken during a logic transition of the divided clock may have voltages insufficient for comparison to the reference clock. Additionally, the voltage sampled during a logic transition of the divided clock may be attributable to the spurs in the divided clock, and not to a desired component of the divided clock at the reference clock frequency. The likelihood that conventional retiming circuits will produce an erroneous retimed clock increases with process and temperature variations.
In view of the foregoing, it would be desirable to provide PLL retiming circuits that are less likely to produce an erroneous retimed clock.